1. Field of the Invention
The present invention relates to a delaying stage selecting circuit and a method thereof, and particularly relates to a delaying stage selecting circuit, which compares each delay signal and a system clock, records the comparing result, and determines a preferred delaying stage according to the comparing result, and a method thereof.
2. Description of the Prior Art
Delay circuits are always utilized in a circuit to synchronize a plurality of clock signals. Conventionally, delay circuits can be classified into analog delay circuits and digital delay circuits.
FIG. 1 is a block diagram illustrating a prior art delay circuit, which can generate a plurality of delayed clock signals of the same frequency but different phase according to an input clock signal CKIN. As shown in FIG. 1, the delay circuit 100 includes: a phase detector 102, a charge pump 104, a loop filter 106, and a delay line 108. A control voltage Vctrl from the loop filter 106 can adjust the delay effect caused by each delaying stage for the input clock signal CKIN. The delayed clock signal from the m-th delaying stage is CKm (m is an integer between I and N) wherein the difference between the delayed clock signal CKN from the last delaying stage and the input clock signal CKIN is Td. The phase detector 102 utilizes the input clock signal CKIN and the delayed clock signal CKN as input signals, and compares the phase difference between both to generate a rising control signal UP and a falling control signal DOWN. The phase detector 102 also utilizes the rising control signal UP and the falling control signal DOWN to control the charge pump 104 in order to control the control signal Vctrl via the loop filter 106, thereby the delay time Td between the input clock signal CKIN and the delayed clock signal CKN can be decreased or increased.
A digital delay circuit can be of various kinds. Normally, a digital circuit includes a delay line having a plurality of delaying stages (flip flops for example), and utilizes a multiplexer or an inverter etc. to control the delaying stages.
The above-mentioned delay circuit generates delay signals with different delay amounts, and a desired delay signal is selected from a plurality of delay signals. Ideally, a desired delay signal needs no adjustment to meet requirements of the system once it is determined and selected. In reality, a delay amount of the delay signal always changes corresponding to many factors such as PVT (Process, Voltage, Temperature), so a system operation error will often occur.